This application claims, under 35 U.S.C. xc2xa7119, the benefit of Korean Patent Application No. 2000-45998, filed on Aug. 8, 2000, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a nonvolatile memory and a system having nonvolatile memories, and more particularly, to a nonvolatile memory, a system having nonvolatile memories, and a data read method of the system that performs a data read operation by interleaving consecutively a plurality of the nonvolatile memories.
2. Description of Related Art
In general, systems having a plurality of memories include a controller to control its operation. However, since such systems use common signal lines to transmit data between the memories and the controller, it is very important in system performance to interleave operation of many memories.
Conventional systems having a plurality of the nonvolatile memories can interleave a plurality of the nonvolatile memories by having a xe2x80x9cdon""t carexe2x80x9d interval during a write or an erase operation. During a read operation, however, it is impossible to interleave a plurality of the nonvolatile memories.
FIG. 1 is a block diagram illustrating a system having a plurality of the nonvolatile memories according to the prior art. As shown in FIG. 1, the system includes a controller 10 and a plurality of nonvolatile memories 20-1 to 20-n. Control signals CLE, ALE, WEB and REB are transmitted from the controller 10 to the nonvolatile memories 20-1 to 20-n through control signal lines 30. Inverted chip enable signals CEB1 to CEBn are transmitted from the controller 10 to the nonvolatile memories 20-1 to 20-n through inverted chip enable signal lines 32. Ready/busy signals RBB1 to RBBn are transmitted from the controller 10 to the nonvolatile memories 20-1 to 20-n through ready/busy signal lines 34. Input/output data IO0 to IOn are transmitted from the controller 10 to the nonvolatile memories 20-1 to 20-n through data input/output lines 36.
The signal CLE is a command latch enable signal that discriminates whether the inputted data are a command. The signal ALE is an address latch enable signal ALE that discriminates whether the inputted data are an address. The signal WEB is an inverted write enable signal that latches all inputted data that are written ( whether a command, an address, or the like). The signals CEB1 to CEBn are inverted chip enable signals that enable a plurality (n in number) of the nonvolatile memories 20-1 to 20-n. The signal REB is a read enable signal that enables a read operation. The signals IO1 to IOn are data that are inputted/outputted to/from the nonvolatile memories 20-1 to 20-n. The signals RBB1 to RBBn are ready/busy signals that indicate internal operation state of the nonvolatile memories 20-1 to 20-n.
FIG. 2 is a block diagram illustrating a configuration of an embodiment of the nonvolatile memory 20-1 of FIG. 1. As shown in FIG. 2, the nonvolatile memory 20-1 includes a memory cell array 40, a row decoder 42, a column decoder 44, a control signal generating circuit 46, a page buffer 48, a data input/output gate 50, and a data input/output buffer 52. The memory cell array 40 includes a plurality of memory cells (not shown) for storing data.
An operation of the nonvolatile memory 20-1 is explained below in detail. The row decoder 42 decodes a row address X, operating under the control of the control signal generating circuit 46. This selects a plurality of word lines (not shown) of the memory cell array 40.
The column decoder 44 decodes a column address Y, operating under the control of the control signal generating circuit 46, and selects the data input/output gate 50. The page buffer 48 stores byte data by one page size, in response to output signals from the column decoder 44
The byte data are inputted through the data input/output gate 50 during the write operation and that are outputted from the memory cell array 40 during the read operation. The data input/output gate 50 transmits data of one page size in byte unit to the data input/output buffer 52 in response to output signals from the column decoder 44. The data input/output buffer 52 buffers data of one page size that are inputted from an external portion, operating under the control of the control signal generating circuit 46, and then outputs to the data input/output gate 50 during the write operation. The data input/output buffer 52 buffers byte data outputted from the data input/output gate 50, outputs the byte data to an external portion during the read operation.
During the write operation, the nonvolatile memory 20-1 stores data of one page size in byte unit inputted from an external portion in the page buffer 48. Then data of one page size stored in the page buffer 48 are transferred to the memory cell array 40.
Conversely during the read operation, data of one page size that are stored in the memory cell array 40 are transferred to the page buffer 48. Then, data of one page size stored in the page buffer 48 are outputted in byte unit through the data input/output gate 50 and the data input/output buffer 52.
That is, the nonvolatile memory 20-1 transfers data to the memory cell array 40, or transfers data to the external portion through the data input/output gate 50 and the data input/output buffer 52. In the process, data become stored in the page buffer 48.
The nonvolatile memory 20-1 generates the ready/busy signal RBB having a logic xe2x80x9chighxe2x80x9d level when control signals, an address and data are inputted from an external portion. Further, the nonvolatile memory 20-1 generates the ready/busy signal RBB having a logic xe2x80x9clowxe2x80x9d level when performing an operation for reading data from the memory cell array 40 to the page buffer 48, and also when performing an operation for write and erase data from the page buffer 48 to the memory cell array 40.
FIG. 3 is a block diagram illustrating an internal inverted chip enable signal generating circuit 59 in the nonvolatile memory 20-1 according to the prior art. Circuit 59 includes a CEB buffer 60, a WEB disable detecting circuit 62, a REB disable detecting circuit 64, a program command detecting circuit 66, an erasing command detecting circuit 68, a read command detecting circuit 70, a PGM DNT signal generating circuit 72, a ERS DNT signal generating circuit 74, a RD DNT signal generating circuit 76, a RBB busy detecting circuit 78, a NOR gate NOR1, a NAND gate NAND1, and an inverter I1.
An operation of the inverted chip enable signal generating circuit is explained below in detail. The CEB buffer 60 buffers the external inverted chip enable signal CEB that is applied from an external portion, and then outputs it. The WEB disable detecting circuit 62 detects a transition of an inverted write enable signal WEB to a logic xe2x80x9chighxe2x80x9d level, and then generates the WEB disable detecting signal. The REB disable detecting circuit 64 detects a transition of the inverted read enable signal REB to a logic xe2x80x9chighxe2x80x9d level, and then generates the REB disable detecting signal. The program command detecting circuit 66 generates a program command detecting signal when a program command 80H is applied. The erase command detecting circuit 68 generates an erase command detecting signal when an erase command 60H is applied. The read command detecting circuit 70 generates a read command detecting signal when read commands 00H, 01H and 50H are applied. The RBB busy detecting circuit 78 detects a busy state of the ready/busy signal RBB and generates a RBB busy detecting signal.
In addition, the PGM DNT signal generating circuit 72 generates a program xe2x80x9cdon""t carexe2x80x9d signal PGM DNT having a logic xe2x80x9chighxe2x80x9d level when the program command detecting signal and the WEB disable detecting signal are generated. The ERS DNT signal generating circuit 74 generates an erasing xe2x80x9cdon""t carexe2x80x9d signal ERS DNT having a logic xe2x80x9chighxe2x80x9d level when the erase command detecting signal and the WEB disable detecting signal are generated.
The RD DNT signal generating circuit 76 generates a read xe2x80x9cdon""t carexe2x80x9d signal RD DNT having a logic xe2x80x9chighxe2x80x9d level when the read command detecting signal, the WEB disable detecting signal and the REB disable detecting signal are generated. Further, the RD DNT signal generating circuit 76 generates the read xe2x80x9cdon""t carexe2x80x9d signal RD DNT having a logic xe2x80x9clowxe2x80x9d level when the RBB busy detecting signal is generated.
The NOR gate NOR1 generates a signal having a logic xe2x80x9clowxe2x80x9d level when at least one of the program xe2x80x9cdon""t carexe2x80x9d signal PGM DNT, the erase xe2x80x9cdon""t carexe2x80x9d signal ERS DNT, and the read xe2x80x9cdon""t carexe2x80x9d signal RD DNT has a logic xe2x80x9chighxe2x80x9d level.
The NAND gate NAND1 and the inverter I1 generate the internal inverted chip enable signal CEiB having a logic xe2x80x9clowxe2x80x9d level in response to a signal having a logic xe2x80x9clowxe2x80x9d signal that is outputted from the NOR gate NOR1.
In other words, when at least one of the program xe2x80x9cdon""t carexe2x80x9d signal PGM DNT, the erasing xe2x80x9cdon""t carexe2x80x9d signal ERS DNT, and the read xe2x80x9cdon""t carexe2x80x9d signal RD DNT has a logic xe2x80x9chighxe2x80x9d level, the internal inverted chip enable signal CEiB having a logic xe2x80x9clowxe2x80x9d level signal is generated. That is regardless of the state of the applied external inverted chip enable signal CEB.
FIG. 4 is a timing diagram illustrating a write operation of the nonvolatile memory 20-1 according to the prior art. In FIG. 4, hatched portions denote the xe2x80x9cdon""t carexe2x80x9d intervals.
The nonvolatile memory 20-1 is enabled to operate in response to the external inverted chip enable signal CEB having a logic xe2x80x9clowxe2x80x9d level. The write command 80H, a starting address, and data are inputted in response to the control signals CLE, WEB and ALE that are applied from an external portion. At this time, the external inverted chip enable signal CEB can enter a xe2x80x9cdon""t carexe2x80x9d state during a logic xe2x80x9chighxe2x80x9d level of the inverted write enable signal WEB by the internal inverted chip enable signal generating circuit of FIG. 3. That is, the nonvolatile memory 20-1 can perform its internal operation independently of the state of the external inverted chip enable signal CEB.
When inputting data is completed, a write starting command 10H is applied from an external portion. The nonvolatile memory 20-1 generates the ready/busy signal RBB having a logic xe2x80x9clowxe2x80x9d level during a busy period tPROG of a write operation. At this time, the external inverted chip enable signal CEB can enter a xe2x80x9cdon""t carexe2x80x9d state during a logic xe2x80x9chighxe2x80x9d level of the inverted write enable signal WEB by the internal inverted chip enable signal generating circuit of FIG. 3. That is, the nonvolatile memory 20-1 can perform its internal operation during a busy period tPROG independently of the external inverted chip enable signal CEB. Therefore, the controller 10 of FIG. 1 can operate other ones of the nonvolatile memories of the chip, even during the busy period tPROG in which the nonvolatile memory 20-1 performs an internal write operation. Even though not shown, it is possible to operate a plurality of the nonvolatile memories even during an erase operation.
FIG. 5 is a timing diagram illustrating a read operation of the nonvolatile memory 20-1 of FIG. 1 according to the prior art. Hatched portions denote the xe2x80x9cdon""t carexe2x80x9d intervals.
The nonvolatile memory 20-1 is enabled to operate in response to the external inverted chip enable signal CEB having a logic xe2x80x9clowxe2x80x9d level. The read command 00H and a starting address are inputted in response to the control signals CLE, WEB and ALE that are applied from an external portion. At this time, the external inverted chip enable signal CEB can enter a xe2x80x9cdon""t carexe2x80x9d state during a logic xe2x80x9chighxe2x80x9d level of the inverted write enable signal WEB by the internal inverted chip enable signal generating circuit of FIG. 3.
When an input of the starting address is completed, the nonvolatile memory 20-1 generates the ready/busy signal RBB having a logic xe2x80x9clowxe2x80x9d level during a busy period tR of a read operation. At this time, the output inverted chip enable signal CEiB can not enter a xe2x80x9cdon""t carexe2x80x9d state during a busy period tR of a read operation by the internal inverted chip enable signal generating circuit 59 of FIG. 3.
This, therefore, is the problem in the prior art, which needlessly slows down the nonvolatile memory chip. The controller 10 of FIG. 1 can not operate any of the other nonvolatile memories in the chip while the nonvolatile memory 20-1 performs an internal read operation (during the busy period tR).
This especially occurs when a sequential read operation and a CEB intercept operation of the nonvolatile memory are performed in the prior art. The sequential read operation is one in which a read operation is performed with sequentially increasing a page from a page corresponding to the starting address, even though a read command and the starting address are inputted only once. The CEB intercept operation is one which disables an operation of the nonvolatile memory by keeping the inverted chip enable signal CEB in the state of a logic xe2x80x9chighxe2x80x9d level during a predetermined interval of a busy period tR. When that happens, the nonvolatile memory according to the prior art cannot enter a xe2x80x9cdon""t carexe2x80x9d state that is regardless of the inverted chip enable signal CEB during a busy period of a read operation.
It is an object of the present invention to provide a nonvolatile memory in which an inverted chip enable signal can enter a xe2x80x9cdon""t carexe2x80x9d state during a first busy period of a read operation.
It is another object of the present invention to provide a system having a plurality of nonvolatile memories that can perform a read operation by interleaving a plurality of the nonvolatile memories.
It is a still further object of the present invention to provide a data read method of the system having a plurality of the nonvolatile memories.
In order to achieve the above object, one of the preferred embodiments of the present invention provides a nonvolatile memory that is adapted to receive an external inverted chip enable signal, and to generate an internal inverted chip enable signal. The memory includes a circuit that generates a first read xe2x80x9cdon""t carexe2x80x9d signal during a disable interval of an inverted write enable signal and a disable interval of an inverted read enable signal when a read command is applied during a read operation, and a second circuit that generates a second read xe2x80x9cdon""t carexe2x80x9d signal that is enabled by detecting an address input end, and disabled by detecting a ready state of a ready/busy signal when the read command is applied during the read operation. The memory also includes a circuit for enabling the internal inverted chip enable signal when at least one of the first and the second read xe2x80x9cdon""t carexe2x80x9d signals is generated, regardless of a logic state of the external inverted chip enable signal.
The invention also provides a method. The invention enables better use of a group of memories by not disabling some of them unnecessarily. This and other features and advantages of the invention will be better understood in view of the accompanying description and detailed drawings.